Software / ASIC Modeling Engineer
We’re working on behalf of a company that is a $20MIL+ leader in Communications ICs, Wireless, Broadband, and Optical. They have a Core Engineering group that supports the Memory Compilers that go into all of their chipsets.
They have a key need in the ASIC Library Development group, where they develop their ASIC models to make design process more efficient. They’re looking for a Software /ASIC Modeling Engineer.
- Will deliver CAD solutions, by means of a Software carrier.
- Neeed a BS/CS EE or better, with 3-10+ years of experience.
- Must be strong in LINUX, and PERL script, which is used extensively. Python useful, as PERL can be learned from there.
- Must also be strong at ASIC / Memory IC Modeling
- Must be very strong with VERILOG as a design simulation tool, and as a Behavioral memory Modeling tool
- Most applicable tool skills are Verilog /RTL and Verilog Behavioral
- This person would understand ASIC Design flows-DFT ( Design for Test) tools, writing Verilog test Benches is on point.
Company has best compensation in semiconductor industry, with very generous bonus and RSUs, and a stock price that has been rapidly advancing.