Signal Integrity Engineer
Our client is a leading maker of ASICs for wireless infrastructure, high speed data networking, and machine learning. They are currently seeking a Signal Integrity Engineer focused on DDR technology.
The ideal candidate will be a BSEE with 8 years of industry experience (or MSEE with 6 years of industry experience). We are looking for someone who will do pre-layout modeling of transceivers and collaborate closely with the Physical Design/Layout team. Additionally we are looking for someone family with 2.5D and 3D spaces, die-die parallel interfaces, HBM (high bandwidth memory), and experience with Python and TCL scripting.