Top-Level Floor Planner Engineer – Physical Design Implementation

POSTING DATE: 9.3.25

We are working with a leader in high speed data center networking and AI applications. They are currently seeking a Floor Planner Engineer to work on Physical Design Implementation for AI ASICs. The ideal candidate will have a BSEE and 6+ years of industry experience in Physical Design implementation. This person will be responsible for top-level floor planning and  interface internally with SoC and Interposer development, packaging, analysis, STA (static timing analysis), and IP while maintaining an aerial or top-level view of the entire physical design implementation process.  Other than the technical attributes of the position, we are looking for someone who can effectively communicate with the customer, especially when the customer is being unrealistic about final designs (i.e. we need an effective communicator who doesn’t have a problem challenging the customer).

• Ideally looking for a BSEE with 6-20 years of experience in Physical Design Implementation.
• Company would consider someone who has done Place and Route, Static Timing Analysis, etc. as long as they are ready to and adaptable to a broader-level role.
• Must have experience with Physical Design tools (Cadence Virtuoso is highly preferred, will also consider someone with Synopsys).
• Also looking for someone who has experience using scripting including Python, TCL, and Linux.